Guide Functional verification coverage measurement and analysis

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The interpretation of the results is different, and by understanding and taking advantage of this difference, you can speed up coverage closure in simulation.

Description

Commonly used code-coverage metrics include line, condition, toggle and finite state machine FSM coverage. Condition coverage monitors whether certain expressions in the code evaluate to true or false. For example, see the Verilog statement below:.

Functional Verification Coverage Measurement and Analysis

Toggle coverage monitors value changes on registers and nets, and measures whether the value has changed from 1 to 0 or from 0 to 1. FSM coverage measures how many FSM states have been visited and how many transitions occur during verification. Each line, condition, register and net which is used for tracking one or more of the coverage metrics is referred to as a coverage goal, and the coverage metric reports the percentage of goals covered.

Please enable cookies in your browser to get the full Trove experience. Skip to content Skip to search. Piziali, Andrew. Published Berlin : Springer, Language English View all editions Prev Next edition 7 of 7.

Stanford Libraries

Author Piziali, Andrew. Physical Description xv, p.

⨘ } VLSI } System Verilog } Quick Overview for Design Verification }

Subjects Integrated circuits -- Design and construction. Integrated circuits -- Verification. Summary 'Addresses a means of quantitatively assessing functional verification progress. Without this process, design and verification engineers, and their management, are left guessing whether or not they have completed verifying the device they are designing. Using the techniques described in this book, they will learn how to build a toolset which allows them to know how close they are to functional closure.

The Language of Coverage.

Understanding SoC Functional Verification Metrics

Functional Verification. Measuring Verification Coverage. Functional Coverage.


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